GSoC'23

This project aims to create a Python-based GUI with a powerful backend system for effective analysis, visualization, and debugging of layout versus schematic (LVS) mismatches in the OpenRAM framework. By processing LVS reports, identifying mismatched nets, and visually displaying discrepancies, the solution will improve debugging efficiency, productivity, and system reliability.

Hi everyone! I’m Manank Patel, and am currently an undergraduate student at Birla Institute of Technology and Sciences - Pilani, KK Birla Goa Campus. As part of the Efficient Communication with Key/Value Storage Devices my proposal under the mentorship of Aldrin Montana and Philip Kufeldt aims to implement io_uring based communication backend for network based key-value store.

Hello everyone! My name is Luiza, I am an eighth-semester Bsc Biological Sciences student from São Paulo, Brazil. As part of the LabOp working group, my proposal under the mentorship of Dan Bryce and Tim Fallon aims to build a conversor that takes normal laboratory protocols and translates them into machine executable protocols.

Hey! I’m Prashant Jha, from Pune, a recent undergraduate student from BITS Pilani. As part of the Polyphy my proposal under the mentorship of Oskar Elek aims to develop and improve the current infrastructure.

Namaste everyone🙏🏻! I’m Nandini Saagar, from Mumbai. An undergraduate student at the Indian Institute of Technology, Banaras Hindu University, IIT (BHU), Varanasi. As part of the Strengthening Underserved Segments of the Open Source Pipeline my proposal under the mentorship of Emily Lovell aims to strengthen the underserved segment of the open source pipeline.